Proteus VSM for PIC Bundle CD

Proteus VSM for PIC16 contains everything you need to develop, test and virtually prototype your embedded system designs based around the Microchip Technologies™ PIC16 series of microcontrollers. The unique nature of schematic based microcontroller simulation with Proteus facilitates rapid, flexible and parallel development of both the system hardware and the system firmware. This design synergy allows engineers to evolve their projects more quickly, empowering them with the flexibility to make hardware or firmware changes at will and reducing the time to market.

• Fully simulates the entire instruction set.
• Supports all port and other I/O pin operations.
• Supports all timers including watchdog timer, sleep mode and wake-up from sleep.
• Supports both Capture-Compare-PWM (CCP) modules in all modes and ECCP modules.
• Supports Parallel Slave Port (PSP) module on appropriate devices.
• Supports MSSP in both the SPI mode and the I2C master and slave modes.
• Supports Analogue-to-Digital Conversion (ADC) module including support for voltage reference pins.
• Supports Analogue Comparator modules including support for internal and external voltage references.
• Supports USART in all modes and EUSART for appropriate variants.
• Supports internal code and data EEPROM memory inc. code protection and data persistence.
• Supports all interrupt modes.
• Supports the LCD controller module in appropriate variants.
• Supports the Ultra Low Power Wake Up module in appropriate variants.
• Internally generated processor clock for performance. Event timing accurate to one clock period.
• Provides internal consistency checks on code (e.g. execution of invalid op-codes, illegal memory accesses, stack overflow checking, etc.).
• Fully integrated in to the VSM source level debugging system.
• Fully integrated into the Proteus Diagnostic Control System.
• Enhanced PIC16 core architecture including Program and Data memory extentions, 14 new instructions, linear mapping, enhanced indirect addressing and automatic interrupt context save.